In modern high density memories, such as random access memories having 2.sup.20 bits (1 Megabit) or more, the time and equipment required to test functionality and timing of all bits in the memory constitutes a significant portion of the manufacturing cost. Accordingly, as the time required for such testing increases, the manufacturing costs also increase. Similarly, if the time required for the testing of the memory can be reduced, the manufacturing cost of the memories is similarly reduced. Since the manufacturing of memory devices is generally done in high volume, the savings of even a few seconds per device can result in significant cost reduction and capital avoidance, considering the high volume of memory devices produced.
Random access memories (RAMs) are especially subject to having significant test costs, not only because of the necessity of both writing data to and reading data from each of the bits in the memory, but also because RAMs are often subject to failures due to pattern sensitivity. Pattern sensitivity failures arise because the ability of a bit to retain its stored data state may depend upon the data states stored in, and the operations upon, bits which are physically adjacent to a particular bit being tested. This causes the test time for RAMs to be not only linearly dependent upon its density (i.e, the number of bits available for storage) but, for some pattern sensitivity tests, dependent upon the square (or 3/2 power) of the number of bits Obviously, as the density of RAM devices increases (generally by a factor of four, from generation to generation), the time required to test each bit of each device in production increases at a rapid rate.
It should be noted that many other integrated circuit devices besides memory chips themselves utilize memories on-chip. Examples of such integrated circuits include many modern microprocessors and microcomputers, as well as custom devices such as gate arrays which have memory embedded therewithin Similar cost pressures are faced in the production of these products as well, including the time and equipment required for testing of the memory portions.
A solution which has been used in the past to reduce the time and equipment required for the testing of semiconductor memories such as RAMs is the use of special "test" modes, where the memory enters a special operation different from its normal operation. In such test modes, the operation of the memory can be quite different from that of normal operation, as the operation of internal testing can be done without being subject to the constraints of normal operation.
An example of a special test mode is an internal "parallel", or multi-bit, test mode. Conventional parallel test modes allow access to more than one memory location in a single cycle, with common data written to and read from the multiple locations simultaneously. For memories which have multiple input/output terminals, multiple bits would be accessed in such a mode for each of the input/output terminals, in order to achieve the parallel test operation. This parallel test mode of course is not available in normal operation, since the user must be able to independently access each bit in order to utilize the full capacity of the memory. Such parallel testing is preferably done in such a way so that the multiple bits accessed in each cycle are physically separated from one another, so that there is little likelihood of pattern sensitivity interaction among the simultaneously accessed bits. A description of such parallel testing may be found in McAdams et al., "A 1-Mbit CMOS Dynamic RAM With Design-For-Test Functions", IEEE Journal of Solid-State Circuits, Vol SC-21, No. 5 (October 1986), pp. 635-642.
As described in this article, conventional parallel test operations may be done in one of two ways. A first one of these methods merely compares the data state read from each of the multiple simultaneously accessed bits with one another. If all of the simultaneously accessed bits have the same data, the test operation passes. The accuracy of this test is based on the assumption that not all of the bits would fail in the same way at the same time. While such an assumption may not always be valid, such as in the case that the data path circuitry is faulty, this parallel test method can be implemented relatively easily, and the testing of common circuitry such as in the data path can be performed separately, so that the accuracy of the overall test sequence is quite high.
The second method for parallel test, commonly referred to as "expected data parallel test", is performed by comparing the data presented by the accessed bits against one another, and also against the contents of an on-chip register to determine not only that the same data was read from all accessed bits, but also that the data state read was the correct data state. Such a parallel test provides improved accuracy in its result, due to the additional comparison, at a cost of increased on-chip circuitry necessary implemented for its implementation.
For either case, the results of the on-chip comparison must be communicated externally from the chip, for example to automated test equipment that is exercising the chip. In the McAdams et al. article cited hereinabove, in the non-expected data mode, the outputs are driven to a high logic level for a passing parallel test and to a low logic level for a failing parallel test. Accordingly, the actual data state of the storage cells is not output at the output terminals in such a parallel test. In this implementation, if for some reason all of the tested locations had the same data state and if that data state were the incorrect one, the memory would communicate a high logic level at the output, indicating that the test had passed.
In the expected data test, the implementation disclosed in the McAdams et al. article enables the output to match the expected data for passing locations and to present the complement of the expected data for failing locations. However, this requires that the automated test equipment, or end system as the case may be, be able to itself store the expected data and compare it to the data received at the output terminals of the memory device. Accordingly, this adds complexity to the test hardware required for the parallel test in the expected data mode. Alternatively, as described in U.S. Pat. Nos. 4,654,849 and 4,860,259, in the expected data mode a comparator may present, at the output terminal, a first logic level for a pass and a second logic level for a fail, similarly as in the non-expected data mode described above, but of course the actual data state stored by the memory cells would in such a case not be presented at the output.
Another technique for communicating the results of the comparison in parallel test mode is to use a dedicated terminal (e.g., a package pin or bond pad, as the case may be) to communicate the results of the on-chip parallel test comparison This technique is especially useful during functional probe test of the memory, as a dedicated terminal may be accessed when the chip is still in wafer form, prior to its encapsulation or other packaging. However, significant test time also occurs after packaging, during which the parallel test feature is also useful. In order to use a dedicated test result terminal for package test, it is therefore necessary that the package have a pin or other external terminal for this function. Due to the desires of the system designer that the circuit package be as small as possible, with as few connections as possible, the use of a dedicated pin for test result communication is therefore undesirable.
Another known technique for communicating the result of the on-chip parallel test uses an existing terminal, one which has a function during normal operation, to present a data state corresponding to the result of the test. The terminal used is often an address terminal, since one or more of the address bits are "don't cares" in the parallel test mode. The results of the test are communicated at this terminal, for example, by setting a "1" on the terminal if all of the accessed bits presented the same data (and matched the expected data, if appropriate) and a "0" if one or more of the accessed bits had a data state different from the others. However, such an arrangement requires the chip design to incorporate a dual function for a terminal, adding to the circuit complexity, chip size, and perhaps, due to additional loading, adversely affecting device performance.
Another known technique for communicating the parallel test result generates a high impedance state on the output terminal when the comparison is false. Such a technique is described in Shimada et al., "A 46-ns 1-Mbit CMOS SRAM", IEEE Journal of Solid-State Circuits, Vol. 23, No. 1, (Feb. 1988) pp. 53-58. In this technique, applied to a multiple output RAM (such as a by-four or by-eight RAM) where the parallel test is accomplished by simultaneously accessing multiple bits for each output, the output terminal for which the comparison is false is placed in a high-impedance state.
As described in this article relative to FIG. 5, parallel test is accomplished in this device by the simultaneous access of four of the array blocks. The comparison of the data retrieved from the four accessed bits is accomplished by arbiter buffers, which drive lines BUS and BUS.sub.-- in wired-AND fashion. As noted on page 55, since the p-channel pull-up transistors in the arbiter buffers are small, if any of the four selected cells fails (e.g., has a "0" instead of a "1"), both of lines BUS and BUS.sub.-- will be at a low logic level. By the operation of the NAND gates which, in such a case, will provide a "1" input to both of the NORs driving the pull-up and pull-down transistors of the output buffer, such a failure will cause a high-impedance state at the output of the device.
As is evident from this construction, however, it is apparent that the arbiter buffers are connected in series in the data path between the sense amplifiers and the data out terminal both for normal and parallel test modes. Accordingly, the propagation delay required by the arbiter buffers is seen during normal operation, so that an access time penalty is paid in order to implement the parallel test comparison. This penalty is made worse by the construction of the arbiter buffers in such a way that the p-channel pull-up transistors are sufficiently small so that a single n-channel pull-down transistor (in the example of a test failure due to reading a "0" instead of a "1") can pull down line BUS or BUS.sub.-- which is being pulled high by the other three p-channel transistors. This small size for the pull-up devices will, of course, result in a slow transition time for a line BUS or BUS.sub.-- going from a low to a high logic level for a read operation.
The problem discussed hereinabove relative to the small p-channel pull-up transistor will become even worse if the parallel test design goes from a by-four test to a by-eight or wider parallel test operation. This is because a single n-channel transistor must be capable of pulling down a node being pulled up by seven, or fifteen in the case of a by-sixteen test, p-channel pull-up transistors. Accordingly, the scheme described in the Shimada et al. paper will become less useful for wider parallel test operations. Of course, as memories become larger and larger, it will become desirable to test even more bits in parallel.
It is therefore an object of this invention to provide a circuit for communicating the result of a parallel test operation on existing output terminals of the device, but where the data state of a passing test appears at the output terminals.
It is a further object of this invention to communicate this result by way of a high impedance state at the output terminal.
It is a further object of this invention to provide such a circuit in such a manner that the access time of the device in normal operation is not significantly affected by the implementation of the circuit.
It is a further object of this invention to provide such a circuit which can be scaled to increasingly wider parallel test schemes without significantly impacting the normal operating characteristics of the device.
It is a further object of this invention to provide such a circuit which, in test mode, will present the actual stored data in the event of a pass of the test.
It is a further object of this invention to provide such a circuit which can perform the parallel test comparison without requiring the use of complementary data lines carrying a differential signal.
It is a further object of this invention to provide such a circuit which can be used not only on memory integrated circuits for parallel test, but also for test modes on integrated circuits which include memories embedded therewithin.
Other objects and advantages of this invention will become apparent to those of ordinary skill in the art having reference to this specification together with the drawings.